In a synchronous digital circuit, the clock signal provides the timing reference for all operations. In power-sensitive applications it is desirable to keep the switching frequency of this clock signal as low as possible in order to minimize current consumption. However, there are some applications in which a low clock frequency causes problems since a low clock frequency puts a limit on the timing resolution available within the circuit.
An example of such an application is a class-D digital modulator. A class-D digital modulator converts a sampled digital representation of a signal (e.g. audio) into a pulse train where the width of the pulses are controlled such that passing the pulse train through a low-pass filter will recreate the desired analog signal. One of the factors controlling how faithfully the analog signal can be recreated is how accurately the width of the pulses can be controlled. If the pulses are generated directly by logic driven by a low-frequency digital clock signal, the resolution of the pulse width modulator is fundamentally limited.
In a state of the art solution this problem is addressed by using a tapped delay line subsequent to the digital modulator, as is shown in FIG. 1. The delay is controlled by selecting an appropriate tap (in the figure tap1, tap2 or tap3) so as to provide sub clock-cycle accuracy in the output of the PWM modulator (Pulse Width Modulator). The example of the prior art shown in FIG. 1 uses three delay elements D1, D2 and D3 to provide an additional accuracy of 2 bits in the pulse width control.
The delay elements are typically implemented using a chain of standard logic gates, such as inverters. The delay through a logic gate is very much dependent on ambient temperature, voltage and variations in processing of the silicon, which means that it must be possible to adjust the delay elements. This is typically done by adjusting the number of logic gates in the signal path by means of multiplexers or, if finer control is required, by adjusting the drive strength of the logic gates in the signal path. The adjustment is performed by a calibration process, whereby the delay through the delay line is measured in order to calculate adjustment values “cal” for each delay stage.
In accordance with the state of the art, such as disclosed in J. D. Garside et al “Amulet3i—an Asynchronous System-on-chip”, Proc. 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2000, calibration of such a delay line is managed by connecting the delay line in a ring oscillator configuration, in which the output of the delay line is connected via an inverter to the input of the delay line. The oscillation so generated has a period that depends on the delay experienced by the positive and negative flanks of the signal. A large number of cycles of this oscillation are measured and compared with the number of cycles of the system clock, which elapse during the same period. It is necessary to perform the large number of cycles due to the inevitable synchronization between the two asynchronous clocks, which can introduce an error of up to half a clock period. During the time that this calibration is in process, the delay line cannot be used for its normal, intended function, which of course is disadvantageous. Alternatively, two delay lines could be used, using one for the intended function and the other for calibration purposes, and alternate between normal operation mode and calibration mode. However, it would then be necessary to bear the hardware cost of implementing two delay lines. This solution also requires more chip area.
Furthermore, two sources of systematic errors remain in such a measurement, which cannot be mitigated by longer measurement periods. Firstly, the period of oscillation depends on the delays experienced by both positive and negative-going flanks of the signal through the delay line, which delays typically are different. This limits the accuracy with which the calibration of either flank can be performed. Secondly, the additional circuitry and signal paths required for connecting the delay line in the ring oscillator configuration also increases the period of the oscillation, as well as the complexity of the circuit.
It would thus be desirable to be able to simplify and improve the calibration of delay lines.